An FPGA (field-programmable gate array) typically includes configuration memory cells, configuration control elements and a matrix of logic blocks and I/O blocks. The configuration control elements are usually latches forming a configuration latch matrix.
FIG. 1 shows the scheme of a known configuration latch matrix usable in a FPGA. Here, configuration frames are loaded into a frame register 110. A horizontal latch array 100 has outputs 101 and 102 supplying write enable signals to latch columns 131 and, respectively, 132.
When either write enable signal goes high, data present on data lines 111 are loaded into a selected latch column. If write enable output 101 is high then data is loaded into the latch column 131 and if enable output 102 is high then data is loaded into the latch column 132.
FIG. 2 of the accompanying drawings shows the flow diagram for a partial configuration method as described in U.S. Pat. No. 5,781,756. The method includes the following steps:
After the start of frame loading, checking for the end of the bit stream (2.1). If it is not the end of bit stream, retrieving a packet from the bit stream (2.2), checking whether the packet is a skip command or a write command (2.3). If the packet is a skip command, just increasing the address of the memory latch column, and retrieving the next frame (2.6). If it is write command, storing the bit stream in a data register (2.4), strobing the address register to load the data into memory cells (2.5) and incrementing the address (2.6). This process goes on until the end of the bit stream.
Problem with this approach is that if we need to load only few frames, even then we need to load skip or write commands for all the frames. In this case there will be many skip commands. Again if most of the frames are to be loaded again, then there will be write commands or skip commands for all the frames. In this case there will be more write command. It will cause a large configuration time.